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| d a t a sh eet product speci?cation file under integrated circuits, ic02 2001 oct 22 integrated circuits SAA7240 mpeg-2 transport risc processor
2001 oct 22 2 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 contents 1 features 1.1 general 1.2 external interfaces 1.3 cpu-related features 1.4 mpeg-2 system processor (msp) features 1.5 compatibility with other devices 2 general description 2.1 limitation notes 2.2 integrated conditional access module (icam ? ) licensing requirements 3 ordering information 4 block diagrams 5 pinning information 5.1 pinning 5.2 pin description 5.3 pin list in numerical order 6 limiting values 7 handling 8 thermal characteristics 9 dc characteristics 9.1 power saving in sleep and coma modes 9.2 maximum allowable load capacitance on output pins 10 application information 10.1 application examples of the multi-master mode 10.2 memory configurations 11 package outline 12 soldering 12.1 introduction to soldering surface mount packages 12.2 reflow soldering 12.3 wave soldering 12.4 manual soldering 12.5 suitability of surface mount ic packages for wave and reflow soldering methods 13 data sheet status 14 definitions 15 disclaimers 16 purchase of philips i 2 c components 2001 oct 22 3 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 1 features 1.1 general conditional access descrambling digital video broadcasting (dvb) compliant, multi2 compliant and icam a (1) compliant targeted to bskyb 3.00 and canal + basic box 3.02 and web box 1.01 applications stream demultiplexing: transport stream (ts), packetized elementary stream (pes), program stream (ps) and proprietary data streams internal 32-bit mips risc-based cpu, supporting mips16 instruction set and running at 81 mhz low-power sleep modes supported across the chip support for external co-processor 0.25 m m technology power supply of 2.5 v for the core and 3.3 v for the peripherals, to be ttl level compatible comprehensive driver software and development tool support package: sqfp208. 1.2 external interfaces the SAA7240 supports the following external interfaces: versatile transport stream input/output at 13.5 mbytes/s configurable in parallel or serial mode. interfaces to ieee 1394 devices (such as philips pdi 1394 chip-set) in full-duplex mode and to external descramblers through a common interface (ci) device. the following interfaces are supported: C 3 parallel ts input/output ports C 2 parallel ts input/output ports and 3 serial ts ports C 1 parallel ts input/output port and 5 serial ts ports C 6 serial ts input/output ports. a microcontroller extension bus, supporting: C 16-bit and 32-bit data buses C up to 64 mbytes addressing range C synchronous dynamic ram (sdram) interface C dynamic ram interface C read only memory (rom) interface C flash memory interface C interface to various peripherals C synchronous interface to communicate with the integrated mpeg audio video graphics decoder (avgd) saa7215 at 40.5 mhz C large endian and small endian byte addressing C a multi-master mode (master and slave modes). 2-channel direct memory access (dma) for fast block move to/from any memory location up to 12 chip selects available, some can be configured as general purpose ports an ieee 1284 interface (centronics) with dma engine supporting master and slave modes. usable as a general purpose port two uart (rs232) data ports with dma capabilities (at 187.5 kbit/s), including hardware flow control signals rxd, txd, rts and cts for modem support a synchronous serial interface (ssi) to connect an off-chip modem analog front-end an elementary uart with dma capabilities, dedicated to front panel devices for instance two dedicated smart card reader interfaces (iso 7816 compatible) with dma capabilities. one interface is intended for the conditional access and is shared with the integrated conditional access module (icam) when icam is enabled; the second interface may be used for pay-per-view two i 2 c-bus master/slave transceivers with dma capabilities, supporting the standard (100 kbit/s) and fast (400 kbit/s) i 2 c-bus modes 32-bit general purpose port eight interrupt inputs parallel audio video interface to the mpeg avgd decoder saa7215 one pulse width modulated (pwm) output with 8-bit resolution an extended jtag (ejtag) interface for board test support. (1) integrated conditional access module ( icam a ) is an intellectual property of news data system corporation. 2001 oct 22 4 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 1.3 cpu-related features the SAA7240 contains an embedded risc cpu, which incorporates the following features: a 32-bit pr3930 core, running at 81 mhz support for large and small byte addressing modes; is ready for windows a (1) ce and psos a (2) operating systems 8-kbyte 2-way set of associative instruction cache 4-kbyte 4-way set of associative data cache a programmable low-power mode, including wake-up on interrupt a memory management unit (mmu) with 32 odd/even entries and variable page sizes multiply/accumulate/divide unit with fast multiply/accumulate for 16-bit and 32-bit operands two fully independent 24-bit timers and one 24-bit timer, including watchdog facilities a real-time clock unit (active in sleep mode) built-in software debug support unit as part of extended jtag debug interface on-chip sram of 4 kbytes for storing code that needs fast execution. 1.4 mpeg-2 system processor (msp) features a flexible re-router to support many combinations of the transport stream input/output interfaces: C connection to serial or parallel common interface ic C connection to serial or parallel 1394 ic in full-duplex mode C static dual front-end handling of channel decoders C a maximum frequency of up to 13.5 mbytes/s in parallel mode and up to 81 mbits/s in serial mode. a demultiplexer scheme, which is fully compliant with canal + and bskyb specifications: C hardware-based parsing of transport, program and proprietary software data streams. the maximum input rate is 13.5 mbytes/s in parallel mode and 81 mbits/s in serial mode C up to 40, 13-bit packet identifier (pid) filters applied on the pid value. 32 pid filters can be dedicated to filter packets containing sections; four pid filters to filter transport packets header; four pid filters to parse audio, video, teletext and subtitle data C 4 ts/pes packet header filters (filter condition of 3 bytes, including pid value for ts packet header and specific filter condition for pes packet header) C 32 section filters based on a flexible number of filter conditions to retrieve psi, si, private data and epg, etc. each section filter supports 48 filters conditions of 12 bytes; each filter condition can be negated or masked on a bit level C 7 ecm/emm filters stored in on-chip ram for icam implementation (ecm/emm packets are stored in on-chip ram) C flexible 40 channel dma-based storage of the 32 section sub-streams and four ts/pes data sub-streams and 4 ts/pes packet headers in external memory C system time base management with a double counter mechanism for clock control and discontinuity handling C two presentation time stamp (pts)/decoding time stamp (dts) timers C a general purpose/high speed (gp/hs) filter, which can serve as an alternative input from ieee 1394 devices, for example. the ieee 1394 gp/hs mode supports packet insertion and has an internal sram for storing two packets. it can also output either scrambled or descrambled ts to ieee 1394 devices. a real time descrambler, supporting different descrambler algorithms and consisting of four modules: C a control word bank, containing 14 pairs (odd or even) of control words and a default control word C the dvb descrambler core, implementing the stream decipher and block decipher algorithms C the multi2 descrambler algorithm, implementing the cbc and ofb mode descrambling functions. in this mode, the maximum frequency is 9 mbytes/s (72 mbits/s) C the integrated conditional access module (icam), including an iso 7816 compliant uart to interface the conditional access smart card. 1.5 compatibility with other devices the SAA7240 seamlessly interfaces to the integrated mpeg avgd decoder saa7215hs. it is also backward compatible with the other devices of the family. the following modes/combinations are supported: SAA7240 with saa7215hs seamless pinning compatibility with the saa7219hs. (1) windows is a registered trademark of microsoft corporation (2) psos is a registered trademark of wind river systems, inc. 2001 oct 22 5 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 2 general description the SAA7240 is a transport mpeg-2 source decoder designed for application in set-top boxes in a digital video broadcast (dvb) environment. it is targeted to bskyb 3.00 and canal + basic box and web box applications. the device is part of a comprehensive source decoding kit that contains all the hardware and software required to receive and decode mpeg-2 transport streams, including descrambling and demultiplexing. in addition, it includes a pr3930 core, which is a 32-bit mips risc-based cpu core supporting the mips16 instruction set (to reduce memory requirements) and several peripheral interfaces such as uarts, i 2 c-bus units, an iec 1883, and an ieee 1284 (centronics) interface. the SAA7240 is therefore capable of performing all controller tasks in digital television applications. furthermore, the SAA7240 complies with dvb, icam and multi2 descrambler standards. the SAA7240 receives transport streams through a versatile stream input interface capable of handling both byte-parallel and bit-serial streams, in various formats, supporting data streams up to and including 13.5 mbytes/s in parallel mode and 81 mbits/s in serial mode. the data stream is first applied to an on-chip descrambler with a dvb descrambling algorithm, on the basis of 14 control word pairs stored in an on-chip ram. demultiplexing is subsequently applied to the data stream, to separate up to 40 individual data streams. the demultiplexer section includes clock recovery and timebase management. program specific information (psi), service information (si), conditional access (ca) messages and private data are selected and stored in external memory, for subsequent off-line processing by the internal pr3930 cpu core. to support advanced board testing facilities, the SAA7240 includes boundary scan test (bst) hardware, according to the jtag standard. the device features flexible low-power sleep modes, which independently control the activity of each functional block and can sustain set-top box standby functionality, thus eliminating the need for a separate front-panel controller. the SAA7240 requires a supply voltage of 3.3 v for the i/o pads and a supply voltage of 2.5 v for the core. 2.1 limitation notes although the most advanced techniques and sophisticated tools are used during the design and validation phases, some design limitations giving some restrictions for specific applications might be discovered during the characterization of the SAA7240 and during its life time. if such an eventuality occurs, a limitation note will be issued, describing the deviation against the specification and the advised work-around if any. this limitation note, also sometimes called anomaly sheet or bug list, is given to customers when they are in the initial design-in phase. once the design-in is in production phase, customers are informed about any new limitation if the severity is estimated to be high. please contact your nearest philips semiconductor sales office for more information. 2.2 integrated conditional access module (icam ? ) licensing requirements companies planning to use icam a implementation in any final product must obtain a license from news data system corporation before designing such products. additional per-chip royalties may be required and are to be paid by the purchaser to news data system corporation. for information on the integrated conditional access module features, a non-disclosure agreement must be signed with philips semiconductors to get the icam a specification. please contact your nearest philips semiconductor sales office for more information. 3 ordering information type number package name description version SAA7240 sqfp208 plastic shrink quad ?at package, 208 leads (lead length 1.3 mm); body 28 28 34 mm; high stand-off height sot316-1 2001 oct 22 6 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 4 block diagrams u ll pagewidth fce811 pi-bus ctrl input/output router mips pr3930 core data cache instruction cache timer 1 timer 2 dsu ejtag timer 3 (watchdog) audio and video interface buffer pool controller demux and descramblers mmu pwm resetn clk jtag peripheral section extension bus controller and dma card reader SAA7240 uart 01 0 1 0 s m = master peripheral with embedded dma channel s = slave peripheral smm pi-bus m s mm m cpu section pwm msp section (1) ss s 12 pio interface i 2 c-bus ieee 1284 ssi rtc 32 khz interrupt controller 4-kbyte sram gpdata pktdata gpd ieee 1284 interface i 2 c-bus interface pio interface uart interface av pes interface extension bus smart card interface ssi interface ejtag interface fig.1 block diagram. (1) the msp section is shown in more detail in fig.2. 2001 oct 22 7 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 handbook, full pagewidth buffer pool controller with 40 dma channels section filter pi-bus fce824 ts-pes packet filter ts-pes header filter control & status registers pi interface av interface pcr/scr gp/hs mpeg bus multi2 descrambler dvb descrambler pid filter bist controllers input interface pwm interrupt handler ecm/emm filter ca/uart module smart card interface av pes interface ram 4 4 32 input / output router pktdata to / from serial or parallel ports gpd pwm gpdata fig.2 msp block diagram. 2001 oct 22 8 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 5 pinning information 5.1 pinning handbook, halfpage SAA7240hs 1 208 157 53 104 52 156 105 fce812 fig.3 pin configuration. 2001 oct 22 9 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 5.2 pin description table 1 interface signal descriptions symbol pin type description buffer type reset state programmable input/output port pio[0:7]/int[0:7] 105 to 112 i/o i/o lines or interrupt inputs bidirectional; cmos input; 2 ma output drive z pio8 113 i/o i/o line bidirectional; cmos input; 2 ma output drive z pio9 114 i/o i/o line bidirectional; cmos input; 2 ma output drive z pio10/bpn 116 i/o i/o line or bus pre-empt; this requires the bus owner to release the bus after the current transfer bidirectional; cmos input; 2 ma output drive z pio11/vpp 117 i/o i/o line or vpp; control signal for the supply voltage (icam) bidirectional; cmos input; 2 ma output drive z pio12/c8 118 i/o i/o line or io data for conditional access (icam) bidirectional; cmos input; 8 ma output drive; open-drain; z pio13/c4 119 i/o i/o line or io data for conditional access (icam) bidirectional; 8 ma output drive; open-drain z pio14/brn 120 i/o i/o line or bus request input bidirectional; cmos input; 2 ma output drive z pio15/bgn 121 i/o i/o line or bus grant output bidirectional; cmos input; 2 ma output drive z pio[16:31]/d[16:31] 20 to 11, 9 to 4, 2 i/o i/o lines or upper data bus in 32-bit con?guration bidirectional; cmos input; 3-state output; 2 ma output drive z extension bus interface d[0:15] 41 to 28, 25 to 21 i/o lower 16-bit data bus bidirectional; cmos input; 3-state output; 2 ma output drive z a[0:21] 63 to 90 o address bus 3-state output; 2 ma output drive low a[22:25] (1) n.a. address bus extension shared with the ieee 1284 interface n.a. n.a. ras0n 49 o row access strobe for dram and sdram bank 0 3-state output; 2 ma output drive high ras1n/dcs1n 48 o row access strobe for dram and sdram bank 1 or sdram chip select bank 1 3-state output; 2 ma output drive high lcasn/lba#/size0 46 o column access strobe lower byte 3-state output; 2 ma output drive high 2001 oct 22 10 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... mlcasn/baa#/size1 45 o column access strobe mid lower byte 3-state output; 2 ma output drive high mucasn/size2 44 o column access strobe mid upper byte 3-state output; 2 ma output drive high ucasn 42 o column access strobe upper byte 3-state output; 2 ma output drive high wen 62 o write enable 3-state output; 2 ma output drive high dcs0n 47 o chip select for sdram bank 0 3-state output; 2 ma output drive high cs[0:8]n 56 to 50, 60, 61 o chip select 3-state output; 2 ma output drive high cs[10:9]n (1) n.a. chip select extension shared with the ieee 1284 interface n.a. n.a. oen/tsn 58 o output enable or transfer start indication 3-state output; 2 ma output drive high dtack 59 i data termination acknowledge cmos input z clk 91 o 40.5 mhz clock 2 ma output drive t uart 0 interface txd0 142 o uart 0 transmit data line 2 ma output drive high rxd0 141 i uart 0 receive data line cmos input z rtsn0 143 o uart 0 request to send 2 ma output drive high ctsn0 144 i uart 0 clear to send cmos input z uart 1 and ssi interface txd1/v34_txd (2) 138 o transmit data line or transmit serial data to the codec 2 ma output drive high rxd1/v34_rxd (2) 137 i receive data line or receive serial data from codec cmos input z rtsn1/v34_fs (2) 139 i/o request to send (output) or frame synchronization reference from codec (input) bidirectional; cmos input; 2 ma output drive high ctsn1/v34_clk (2) 140 i clear to send or serial input clock from codec (up to 3.375 mhz) cmos input z mclk 146 o master clock to the codec (up to 36.864 mhz) 2 ma output drive t uart 2 interface txd2 136 o uart 2 transmit data line 2 ma output drive high rxd2 135 i uart 2 receive data line cmos input z symbol pin type description buffer type reset state 2001 oct 22 11 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... i 2 c-bus 0 interface sda0 150 i/o data line bidirectional; cmos input; open-drain; 8 ma output drive z scl0 149 i/o clock line bidirectional; cmos input; open-drain; 8 ma output drive z i 2 c-bus 1 interface sda1 148 i/o data line bidirectional; cmos input; open-drain; 8 ma output drive z scl1 147 i/o clock line bidirectional; cmos input; open-drain; 8 ma output drive z smart card 0 interface sc_i/o0 134 i/o i/o line bidirectional; cmos input; open-drain; 8 ma output drive z clk_card0 128 o clock to the card 2 ma output drive low cmdvccn0 129 o command of the card power supply 2 ma output drive high rstin0 132 o reset of the card 2 ma output drive high offn0 133 i card presence detection cmos input z smart card 1 interface sc_i/o1 126 i/o i/o line bidirectional; cmos input; open-drain; 8 ma output drive z clk_card1 122 o clock to the card 2 ma output drive low cmdvccn1 123 o command of the card power supply 2 ma output drive high rstin1 124 o reset of the card 2 ma output drive high offn1 125 i card presence detection cmos input z parallel or serial transport input interface from the front-end pktdata[0:7] 164 to 157 i 8-bit primary ts data input cmos input z pktstrobe 154 i/o byte strobe or bit strobe bidirectional; cmos input; 2 ma output drive z pktvalid 156 i data valid or bit stream word select cmos input z pktsync 155 i packet synchronization z symbol pin type description buffer type reset state 2001 oct 22 12 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... gp/hs interface (1 parallel port or 2 serial ports) gpdata[0:7] 174 to 166 i/o gp/hs data bus bidirectional; cmos input; 2 ma output drive z gpsync 176 i/o gp/hs synchronization bidirectional; cmos input; 2 ma output drive z gpvalid 175 i/o gp/hs valid bidirectional; cmos input; 2 ma output drive z gpstrobe 177 i/o gp/hs strobe bidirectional; cmos input; 2 ma output drive z audio/video interface avd0/strap0 103 i/o mpeg audio/video data stream output port 0; latched in pio_strap register during reset bidirectional; cmos input; 3-state output; 2 ma output drive z avd1/strap1 102 i/o mpeg audio/video data stream output port 1; latched in pio_strap register during reset bidirectional; cmos input; 3-state output; 2 ma output drive z avd2/strap2 101 i/o mpeg audio/video data stream output port 2; latched in pio_strap register during reset bidirectional; cmos input; 3-state output; 2 ma output drive z avd3/strap3 100 i/o mpeg audio/video data stream output port 3; latched in pio_strap register during reset bidirectional; cmos input; 3-state output; 2 ma output drive z avd4/big 99 i/o mpeg audio/video data stream output port 4; latched in pio_strap register during reset bidirectional; cmos input; 3-state output; 2 ma output drive z avd5/bootcs0 98 i/o mpeg audio/video data stream output port 5; latched in pio_strap register during reset bidirectional; cmos input; 3-state output; 2 ma output drive z avd6/bootw1 97 i/o mpeg audio/video stream data output port 6; latched in pio_strap register during reset bidirectional; cmos input; 3-state output; 2 ma output drive z avd7/bootw0 96 i/o mpeg audio/video stream data output port 7; latched in pio_strap register during reset bidirectional; cmos input; 3-state output; 2 ma output drive z a_strobe 94 o audio data strobe in the avd stream 2 ma output drive low v_strobe 93 o video data strobe in the avd stream 2 ma output drive low av_error 95 o ?ag for bit stream error (active high) 2 ma output drive low symbol pin type description buffer type reset state 2001 oct 22 13 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... ieee 1284 or transport stream interface gpd0/ts_dat0 190 i/o parallel data bus or data for serial tss2_in interface bidirectional; cmos input; 2 ma output drive z gpd1/ts_syn0 191 i/o parallel data bus or sync for serial tss2_in interface bidirectional; cmos input; 2 ma output drive z gpd2/ts_val0 192 i/o parallel data bus or data valid for serial tss2_in interface bidirectional; cmos input; 2 ma output drive z gpd3/ts_ck0 193 i/o parallel data bus or clock for serial tss2_in interface bidirectional; cmos input; 2 ma output drive z gpd4/ts_val1 194 i/o parallel data bus or data valid for serial ci_out interface bidirectional; cmos input; 2 ma output drive z gpd5/ts_syn1 195 i/o parallel data bus or sync for serial ci_out interface bidirectional; cmos input; 2 ma output drive z gpd6/ts_dat1 196 i/o parallel data bus or data for serial ci_out interface bidirectional; cmos input; 2 ma output drive z gpd7/ts_ck1 197 i/o parallel data bus or clock for serial ci_out interface bidirectional; cmos input; 2 ma output drive z nselectin/ts_dat2 199 i/o host to peripheral select line or data for serial ci_in interface bidirectional; cmos input; 2 ma output drive z ninit/ts_syn2 200 i/o host to peripheral control line or sync for serial ci_in interface bidirectional; cmos input; 2 ma output drive z nstrobe/ts_val2 201 i/o host to peripheral strobe line or data valid for serial ci_in interface bidirectional; cmos input; 2 ma output drive z nack/cs10n/ts_ck2 202 i/o peripheral acknowledge line or clock for serial ci_in interface or chip select bidirectional; cmos input; 3-state output; 2 ma output drive z busy/cs9n 203 i/o peripheral busy line or chip select bidirectional; cmos input; 3-state output; 2 ma output drive z perror/a25 204 i/o peripheral error or address line bidirectional; cmos input; 3-state output; 2 ma output drive z select/a24 205 i/o peripheral on-line or address line bidirectional; cmos input; 3-state output; 2 ma output drive z nautof/a23 206 i/o peripheral error line or address line bidirectional; cmos input; 3-state output; 2 ma output drive z symbol pin type description buffer type reset state 2001 oct 22 14 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... nfault/a22 207 i/o host to peripheral control line or address line bidirectional; cmos input; 3-state output; 2 ma output drive z dir1284 208 o direction control of the external buffers 2 ma output drive low pwm interface pwm0 165 o pwm output for vcxo control open-drain; 8 ma output drive low system interface resetn 1 i/o general system reset; active low; the pad is asserted low (if enabled) when the internal watch dog time-out is detected bidirectional; cmos input; 4 ma output drive open drain; low xtal1 153 i 13.5 mhz crystal input oscillator input t xtal2 152 i/o 13.5 mhz crystal output or external clock input oscillator output t jtag and test interface tdo 178 o test data output/target pc output 2 ma output drive z tdi 179 i test data input/debug interrupt cmos input z tms 180 i test mode select cmos input z trst 181 i test reset cmos input z tck 184 i test clock cmos input z ejtag interface dsu_clk 185 o dsu clock is equivalent to the processor clock; used to capture address and data from pin tdo when pc trace mode is on; is 3-stated when bit 0 or 15 of the jtag_control_register is low or logic 0 2 ma output drive z pcst[0:2] 186 to 189 o cpu status (debug mode, pipeline stall and occurrence of exception) 2 ma output drive z symbol pin type description buffer type reset state 2001 oct 22 15 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... notes 1. these signals are internal. 2. shared with uart 1 and ssi. power supplies v dda 151 s 2.5 v analog supply voltage for the pll and oscillator n.a. v ddc 27, 79, 130, 182 s 2.5 v supply voltage for the core n.a. v ddp 3, 17, 31, 43, 66, 80, 92, 115, 145, 187 s 3.3 v supply voltage for interface i/o pads n.a. v ssc 26, 78, 131, 183 s ground for the core n.a. v ssp 10, 23, 37, 57, 72, 86, 104, 127, 170, 190 s ground for the interface pads n.a. symbol pin type description buffer type reset state 2001 oct 22 16 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 5.3 pin list in numerical order table 2 numbered list of SAA7240 pins pin name 1 resetn 2 pio31/d31 3, 17, 31, 43, 66, 80, 92, 115, 145, 187 v ddp 4 pio30/d30 5 pio29/d29 6 pio28/d28 7 pio27/d27 8 pio26/d26 9 pio25/d25 10, 23, 37, 57, 72, 86, 104, 127, 170, 198 v ssp 11 pio24/d24 12 pio23/d23 13 pio22/d22 14 pio21/d21 15 pio20/d20 16 pio19/d19 18 pio18/d18 19 pio17/d17 20 pio16/d16 21 d15 22 d14 24 d13 25 d12 26, 78, 131, 183 v ssc 27, 79, 130, 182 v ddc 28 d11 29 d10 30 d9 32 d8 33 d7 34 d6 35 d5 36 d4 38 d3 39 d2 40 d1 41 d0 42 ucasn 44 mucasn/size2 45 mlcasn/baa#/size1 46 lcasn/lba#/size0 47 dcs0n 48 ras1n/dcs1n 49 ras0n 50 cs6n 51 cs5n 52 cs4n 53 cs3n 54 cs2n 55 cs1n 56 cs0n 58 oen/tsn 59 dtack 60 cs7n 61 cs8n 62 wen 63 a0 64 a1 65 a2 67 a3 68 a4 69 a5 70 a6 71 a7 73 a8 74 a9 75 a10 76 a11 77 a12 81 a13 82 a14 83 a15 84 a16 85 a17 87 a18 88 a19 89 a20 90 a21 pin name 2001 oct 22 17 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 91 clk 93 v_strobe 94 a_strobe 95 av_error 96 avd7/bootw0 97 avd6/bootw1 98 avd5/bootcs0 99 avd4/big 100 avd3/strap3 101 avd2/strap2 102 avd1/strap1 103 avd0/strap0 105 pio0/int0 106 pio1/int1 107 pio2/int2 108 pio3/int3 109 pio4/int4 110 pio5/int5 111 pio6/int6 112 pio7/int7 113 pio8 114 pio9 116 pio10/bpn 117 pio11/vpp 118 pio12/c8 119 pio13/c4 120 pio14/brn 121 pio15/bgn 122 clk_card1 123 cmdvccn1 124 rstin1 125 offn1 126 sc_i/o1 128 clk_card0 129 cmdvccn0 132 rstin0 133 offn0 134 sc_i/o0 135 rxd2 136 txd2 137 rxd1/v34_rxd pin name 138 txd1/v34_txd 139 rtsn1/v34_fs 140 ctsn1/v34_clk 141 rxd0 142 txd0 143 rtsn0 144 ctsn0 146 mclk 147 scl1 148 sda1 149 scl0 150 sda0 151 v dda 152 xtal2 153 xtal1 154 pktstrobe 155 pktsync 156 pktvalid 157 pktdata7 158 pktdata6 159 pktdata5 160 pktdata4 161 pktdata3 162 pktdata2 163 pktdata1 164 pktdata0 165 pwm0 166 gpdata7 167 gpdata6 168 gpdata5 169 gpdata4 171 gpdata3 172 gpdata2 173 gpdata1 174 gpdata0 175 gpvalid 176 gpsync 177 gpstrobe 178 tdo 179 tdi 180 tms pin name 2001 oct 22 18 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 181 trst 184 tck 185 dsu_clk 186 pcst0 188 pcst1 189 pcst2 190 gpd0/ts_dat0 191 gpd1/ts_syn0 192 gpd2/ts_val0 193 gpd3/ts_ck0 194 gpd4/ts_val1 195 gpd5/ts_syn1 pin name 196 gpd6/ts_dat1 197 gpd7/ts_ck1 199 nselectin/ts_dat2 200 ninit/ts_syn2 201 nstrobe/ts_val2 202 nack/cs10n/ts_ck2 203 busy/cs9n 204 perror/a25 205 select/a24 206 nautof/a23 207 nfault/a22 208 dir1284 pin name 2001 oct 22 19 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 6 limiting values in accordance with the absolute maximum rating system (iec 60134). notes 1. system designers should be aware that: a) the ic junction temperature (t j ) is greatly influenced by the environment and the printed-circuit board (pcb) layout thermal behaviour. total allowable power p tot in the customer application depends on its thermal characteristics; thermal resistance from junction to air; (r th(j-a) , refer to chapter 8) and ambient temperature t amb . p tot(max) =(t j(max) - t amb )/r th(j-a) =p int +p i/o . p int represents the internal device power (core and pll). p i/o is the power dissipation in the input and output buffers. p int depends on the user application and is limited by the maximum drive capability of the output buffers. b) table 3 gives some examples of theoretical maximum power dissipation supported by the package; the designer has to check that there is no i ddp maximum current violation. 2. this value represents the maximum current that the power track can carry without excessive voltage drop in the internal chip. this value does not reflect the maximum current consumption of the core, which is far below this value. 3. this theoretical maximum value which should never be exceeded is determined when all output buffers are driving their specified maximum static drive current. in a standard application, this worst case never occurs because the output loads are mainly line capacitance and not resistive loads. 7 handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling cmos integrated circuits. 8 thermal characteristics note 1. when the device is soldered onto a pcb, the intrinsic thermal resistance of the package is improved. the r th(j-a) value depends on the pcb type; some typical values are given below: a) for a standard pcb; r th(j-a) =32 c/w. b) for a 4-layer pcb; r th(j-a) =28 c/w. c) for a 4-layer pcb with thermal dissipation layer; r th(j-a) =24 c/w. symbol parameter min. max. unit v ddp supply voltage for the i/o buffers - 0.5 4.0 v v ddc , v dda supply voltages for the core, pll and oscillator - 0.5 3.0 v v i input voltage on any pin with respect to ground (v ss ) - 0.5 v dd + 0.5 v p tot total power dissipation (based on package transfer, not ic power consumption) - p tot(max) (1) w i ddc core supply current - 500 (2) ma i ddp supply current for the i/o buffers - 330 (3) ma t stg storage temperature - 55 150 c t amb ambient temperature 0 70 c t j junction temperature - 125 c symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 35 (1) c/w 2001 oct 22 20 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 table 3 theoretical package maximum power dissipation 9 dc characteristics v ddp = 3.0 to 3.6 v; v ddc = 2.25 to 2.75 v; v dda = 2.25 to 2.75 v; v ss =0v; t amb = 0 to 70 c; all voltages with respect to v ss ; unless otherwise speci?ed. notes 1. typical current measured on a test board running a set-top box-like application (bitstream decoding and a few on-chip peripherals activated). 2. the typical current in sleep and coma modes is given in table 4. thermal coefficient (r th(j-a) ) p tot(max) at t amb =70 cp tot at t amb =50 cp tot at t amb =25 c 35 c/w 1.57 w 2.14 w 2.85 w 32 c/w 1.72 w 2.34 w 3.12 w 28 c/w 1.96 w 2.67 w 3.57 w 24 c/w 2.29 w 3.26 w 4.34 w symbol parameter conditions min. typ. max. unit v ddp supply voltage for the i/o buffers 3.0 3.3 3.6 v v ddc supply voltage for the core 2.25 2.5 2.75 v v dda analog supply voltage for pll and oscillator 2.25 2.5 2.75 v i ddp supply current for the interface i/o pads v ddp = 3.3 v - 30 (1) - ma i ddc core supply current v ddc = 2.5 v - 220 (2) - ma i dda analog supply current v dda = 2.5 v; f clk = 13.5 mhz - 2 (2) - ma i ddc(sleep) core supply current in sleep mode values are measured at v dd(max) ; f clk = 13.5 mhz - (2) - ma i ddc(coma) core supply current in coma mode - (2) - ma inputs v il low-level input voltage -- 0.8 v v ih high-level input voltage (except xtal1) 2.0 - v ddp + 0.5 v v ih(xtal1) high-level input voltage (xtal1) 2.0 - 2.5 v i il input leakage current v dd = 3.3 v; v ss 2001 oct 22 22 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 10 application information handbook, full pagewidth fce815 adac tda8004 smart cards telco interface flash dram (optional) vxx modem ieee1394 l + phy buffers ieee 1284 rs232 ieee 1394 16-mbit sdram 16-mbit sdram (optional) front panel control saa8044 (sdd) tda8060 tda5056 tuner switching scart1 scart2 scart3 saa7215 SAA7240 av pes mpeg-2 i 2 c-bus rf-in 2 lr rgb cvbs/yc fig.4 set-top box example. 2001 oct 22 23 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 10.1 application examples of the multi-master mode the SAA7240 supports a multi-master mode. the SAA7240 is always the bus arbiter of the external bus interface unit (ebiu) bus. the possible configurations are depicted in figs 5 and 6. handbook, full pagewidth rom flash sdram peripheral gateway saa7215 SAA7240 bpn bgn brn av pes fce813 ebiu bus co-processor 16-mbit video 16-mbit graphics fig.5 multi-master mode; ebiu bus is shared with a co-processor. handbook, full pagewidth rom flash sdram peripheral co-processor gateway 16-mbit video 16-mbit graphics saa7215 SAA7240 bpn bgn brn av pes fce814 ebiu bus saa7215 bus fig.6 multi-master mode; ebiu bus is split with a co-processor. 2001 oct 22 24 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 10.2 memory con?gurations figures 7 and 8 show some examples of typical set-top box memory configurations. handbook, full pagewidth fce816 SAA7240 saa7215 dram/ sdram sdram (mpeg) prom 16 8 16 flash reserved 16 16 fig.7 typical low-end memory configuration; data bus is 16 bits wide. handbook, full pagewidth fce817 SAA7240 saa7215 dram/ sdram sdram (mpeg) prom 32 32 16 16 flash-1 flash-2 16 16 sdram graphics fig.8 typical high-end configuration; data bus is 32 bits wide. 2001 oct 22 25 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 11 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.50 0.25 3.6 3.2 0.25 0.27 0.17 0.20 0.09 28.1 27.9 0.5 30.9 30.3 1.39 1.11 8 0 o o 0.08 0.2 1.3 0.08 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot316-1 ms-029 99-12-27 00-01-25 d (1) (1) (1) 28.1 27.9 h d 30.9 30.3 e z 1.39 1.11 d pin 1 index b p e q e a 1 a l p detail x l (a ) 3 b 52 c d h b p e h a 2 v m b d z d a z e e v m a x 1 208 157 156 105 104 53 y w m w m 0 5 10 mm scale 208 leads (lead length 1.3 mm); body 28 x 28 x 3.4 mm; high stand-off height sqfp208: plastic shrink quad flat package; sot316-1 a max. 4.10 2001 oct 22 26 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 12 soldering 12.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 12.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 12.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 12.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 2001 oct 22 27 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 12.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, hbga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable 2001 oct 22 28 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 13 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. 14 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 15 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. ics with mpeg-2 functionality ? use of this product in any manner that complies with the mpeg-2 standard is expressly prohibited without a license under applicable patents in the mpeg-2 patent portfolio, which license is available from mpeg la, l.l.c., 250 steele street, suite 300, denver, colorado 80206. 2001 oct 22 29 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 16 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 2001 oct 22 30 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 notes 2001 oct 22 31 philips semiconductors product speci?cation mpeg-2 transport risc processor SAA7240 notes ? koninklijke philips electronics n.v. 2001 sca73 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753504/01/pp 32 date of release: 2001 oct 22 document order number: 9397 750 07749 |
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